a) Field of the Invention
The present invention relates generally to an amplitude modulation circuit and method using power amplifiers, and more particularly to an amplitude modulation circuit which contributes to down-sizing, power saving, and improvement in quality of a full solid state MF (medium frequency) radio broadcaster. The present invention relates further to an amplitude modulation circuit applicable to a wide variety of broadcasters ranging from low power of 100 watts output level to medium and high power.
b) Description of the Related Arts
A typical digital amplitude modulation circuit suitable for a full solid state MF radio broadcaster is described in, for example, HOSO GIJUTSU, April, 1991. This circuit includes a total of 48 power amplifiers, that is, 42 big step modules and 6 binary modules. The binary modules have respective outputs equal to 1/2, 1/4, 1/8, 1/16, 1/32 and 1/64 of those of the big step modules. A 12-bit digital signal is derived from A/D (analog-to-digital) conversion of an input program sound signal, 6 bits on the MSB (most significant bit) side being used for on/off control of outputs of the 42 big step modules and 6 bits on the LSB (least significant bit) side being used for on/off control of outputs of the 6 binary modules. The outputs of all the big step modules and of all the binary modules are then power combined to obtain a high power signal whose amplitude has been modulated in accordance with the program sound signal.
The thus configured amplitude modulation circuit, however, disadvantageously needs as many as 48 power amplifiers in total. Use of such a multiplicity of power amplifiers would lead to a complicated and large-scale configuration of the amplitude modulation circuit. In other words, it would be inappropriate to use such type of amplitude modulation circuit for a low output broadcaster. In addition, a power supply voltage for driving the binary modules having a lower output as compared with the big step modules must be lower than that for the big step modules, and a power supply voltage for driving relatively low output binary modules must be lower than that for relatively high output binary modules. That is, parallel use of power amplifiers having different outputs would necessitate the use of a multiplicity of power supplies whose output voltages are different.
In order to obviate the above disadvantage, use may be made of, for example, a circuit described in Japanese Patent Laid-open Pub. No. Hei 5-63458. The circuit disclosed in this official gazette is schematically shown in FIG. 5. This circuit comprises an A/D converter 10 for analog-to-digital conversion of an input program sound to generate a 12-bit digital signal; 16 digital power amplifiers 12-1, 12-1, . . . 12-16; and an analog power amplifier 14. The digital power amplifiers 12-1, 12-2, . . . 12-16 serve to amplify a carrier with frequency f.sub.0 outputted from an RF (radio frequency) carrier oscillator 20.
The upper 4 bits of the 12-bit digital signal generated by the A/D converter 10 are converted into a 16-bit digital signal by means of a gate circuit 16. Each bit of the 16-bit digital signal obtained through the gate circuit 16 is correlated with any one of the power amplifiers 12-1, 12-2, . . . 12-16 and is used for on/off control of the output of a corresponding one of the power amplifiers 12-1, 12-2, . . . 12-16.
The lower 8 bits of the 12-bit digital signal generated by the A/D converter 10 are converted into an analog signal by means of a D/A (digital-to-analog) converter 18. The analog signal obtained through the D/A converter 18 is used for gain control of the power amplifier 14.
A carrier amplified by the power amplifier whose output is currently on among the power amplifiers 12-1, 12-2, . . . 12-16 and a carrier amplified by the power amplifier 14 are fed to the primary windings of a corresponding one of a total of 17 output transformers constituting a power combiner 22. The power combiner 22 is so configured that the secondary windings of these output transformers are connected in series. Accordingly, between the oppositing two ends of this series connection there appears an amplitude modulated wave, namely, a signal having a waveform obtained by combining the output of the digital power amplifier whose output is now on with the output of the analog power amplifier. A BPF 24 extracts from this amplitude modulated wave only components having frequencies in the vicinity of f.sub.0, and supplies the thus extracted components as an output of the broadcaster to another circuit which follows.
In this manner, the circuit depicted in FIG. 5 does not need as many as 48 power amplifiers and therefore it eliminates the necessity of preparing a multiplicity of power supplies having different output voltage specifications as power supplies for driving the respective power amplifiers. This also leads to a reduction in size of the configuration of the amplitude modulation circuit and therefore of the circuit configuration of the entire broadcaster incorporating that amplitude modulation circuit. In the circuit configuration depicted in FIG. 5, however, it is still necessary to prepare a multiplicity of power amplifiers amounting to 17. If the number of power amplifiers is decreased while maintaining such a configuration for controlling the digital power amplifiers using the upper bits of the digitized program sound signal and controlling the analog power amplifier using the lower bits, there may possibly be increased distortion at junctures between outputs of the respective power amplifiers at the time of power combining, that is, distortion resulting from quantization.